1. Field of the Invention:
The present invention relates to a vertical MOS field effect transistor (hereinafter, refer to V-MOS FET), and more particularly to a structural improvement of the V-MOS FET for high withstand voltage and high switching speed.
2. Description of the Related Art:
The V-MOS FET for high power use has a plurality of N (or P) type base regions at a surface of a P (or N) type drain substrate. P (or N) type source regions are respectively formed in the N (or P) type base regions. A mesh-shape gate is formed on a surface region between the source regions to cover exposed drain region and the base regions between the source regions and the exposed drain region via an insulating gate film. A source electrode is formed on the surface of the substrate to contact with the source and base regions. A drain electrode is formed on a back surface of the substrate.
In response to a signal voltage at the gate electrode, conductive channels are induced at surfaces of the base regions between the source regions and the exposed drain regions. Current flows from the source electrode on the surface to the drain electrode on the back surface through the channels. The V-MOS FET has a very wide channel width to have a large current capacity. Thus, the V-MOS FET is preferable to be used in a high power use.
ON-resistance of the V-MOS FET is primarily determined by a resistivity of drain region between the base regions through which current flows vertically. Therefore, the wider is the interval between the base regions, the smaller is the ON-resistance. On the other hand, the gate electrode operates as a field electrode for extending depletion regions from the base regions when voltage between the source and drain regions becomes large While the condition where the intervals between the base regions are filled with the depletion regions exhibit the highest withstand voltage, wide interval between the base regions makes the depletion regions separate to decrease the withstand voltage between the source (or base) and drain regions. Thus, the interval between the base regions is determined by a compromise between the ON-resistance and the withstand voltage.
The mesh-shape gate V-MOS FET has a demerit. The interval between the base regions is widest under crossing point between rows and columns of the gate electrode. Therefore, if the intervals between parallel opposing base regions are filled with the depletion region by a high source-drain voltage, the interval between diagonally opposing base regions are not filled with depletion region. The total withstand voltage is determined by that at the intervals between diagonally opposing base regions. In other words, for obtaining a predetermined total withstand voltage, the interval between the diagonally opposing base regions should be selected to have such predetermined withstand voltage. The intervals between parallel opposing base regions become shorter than the interval determined by the predetermined withstand voltage. Thus, ON-resistance which is determined by the intervals between the parallel opposing base regions becomes an unnecessarily high value.
Another demerit of the mesh-shape gate V-MOS FET is a limited maximum operation speed. The gate electrode covers all the surface of the drain substrate exposed from the base regions. This wide coverage produces a large gate-drain stray capacitance. For changing a conductive condition of the V-MOS FET, this gate-drain stray capacitance must be charged or discharged. Due to these charging and discharging, the maximum switching speed is limited to a slow value.